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FDG6301N - Dual N-Channel/ Digital FET

General Description

These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.

This very high density process is especially tailored to minimize on-state resistance.

Key Features

  • 25 V, 0.22 A continuous, 0.65 A peak. RDS(ON) = 4 Ω @ VGS= 4.5 V, RDS(ON) = 5 Ω @ VGS= 2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package. SC70-6 SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 D1 G2 S2 1 or 4.
  • .01 2 or 5 6 or 3 SC70-6 S1 G1 D2 3 or 6 5 or 2 4 or 1.
  • The pinouts are symmetrical;.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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July 1999 FDG6301N Dual N-Channel, Digital FET General Description These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Features 25 V, 0.22 A continuous, 0.65 A peak. RDS(ON) = 4 Ω @ VGS= 4.5 V, RDS(ON) = 5 Ω @ VGS= 2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package.