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SUMMARY
● Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle ● Mobile DDR SDRAM INTERFACE - x32 bus width - Multiplex...
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SUMMARY
HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications MULTIPLANE ARCHITECTURE - Array is split into two in...
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• ADC module: - Configurable as 10-bit, 1.1 Msps with four S&H or 12-bit, 500 ksps with one S&H - Six analog inputs on 28-pin devices and up to 16 ana...