Product status link M54HCxxx, M54HCTxxx M54HCxxx,.
54HC109 - Rad-hard high speed 2 to 6V CMOS logic
Product status link M54HCxxx, M54HCTxxx M54HCxxx, M54HCTxxx Datasheet Rad-hard high speed 2 to 6 V CMOS logic series Features • ESCC qualified • 7 V .54HC10 - Triple 3-Input NAND Gates
CD74HC10, CD54HC10 SCHS128D – AUGUST 1997 – REVISED JULY 2021 CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltag.54HC10 - Rad-hard high speed 2 to 6V CMOS logic
Product status link M54HCxxx, M54HCTxxx M54HCxxx, M54HCTxxx Datasheet Rad-hard high speed 2 to 6 V CMOS logic series Features • ESCC qualified • 7 V .CD54HC109 - Dual J-K Flip-Flop
Data sheet acquired from Harris Semiconductor SCHS140E March 1998 - Revised October 2003 CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Dual J-K Flip-F.SN54HC10 - TRIPLE 3-INPUT POSITIVE-NAND GATES
www.ti.com SCLS083E – DECEMBERSS1NN9877244–HHRCCEV11I00S,,ESSDNNAP55R44IHHL CC20112001 SCLS083E – DECEMBER 1982 – REVISED APRIL 2021 SNx4HC10 Triple .SNJ54HC109J - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
D Wide Operating Voltage Range of 2 V to 6 V D Low Input Current of 1 µA Max D High-Current Outputs Drive Up To 10 LSTTL Loads SN54HC109 . . . J OR W .SN54HC109 - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
SN54HC109, SN74HC109 SCLS470C – MARCH 2003 – REVISED JUNE 2022 SNx4HC109 Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 1 Features.SN54HC10J - TRIPLE 3-INPUT POSITIVE-NAND GATES
www.ti.com SCLS083E – DECEMBERSS1NN9877244–HHRCCEV11I00S,,ESSDNNAP55R44IHHL CC20112001 SCLS083E – DECEMBER 1982 – REVISED APRIL 2021 SNx4HC10 Triple .M54HC10 - Rad-hard high speed 2V to 6V CMOS logic
Product status link M54HCxxx, M54HCTxxx M54HCxxx, M54HCTxxx Datasheet Rad-hard high speed 2 to 6 V CMOS logic series Features • ESCC qualified • 7 V .54HC109 - Dual J-K Positive-Edge-Triggered Flip-Flops
SN54HC109, SN74HC109 SCLS470C – MARCH 2003 – REVISED JUNE 2022 SNx4HC109 Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 1 Features.M54HC107 - DUAL J-K FLIP FLOP WITH CLEAR
M54HC107 M74HC107 DUAL J-K FLIP FLOP WITH CLEAR . . . . . . . . HIGH SPEED fMAX = 75 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.).CD54HC107 - Dual J-K Flip-Flop
Data sheet acquired from Harris Semiconductor SCHS139D March 1998 - Revised October 2003 CD54HC107, CD74HC107, CD74HCT107 Dual J-K Flip-Flop with Res.CD54HC10 - Triple 3-Input NAND Gates
CD74HC10, CD54HC10 SCHS128D – AUGUST 1997 – REVISED JULY 2021 CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltag.SNJ54HC10FK - TRIPLE 3-INPUT POSITIVE-NAND GATES
D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC SN54HC10 . . . J OR W PAC.SNJ54HC10W - TRIPLE 3-INPUT POSITIVE-NAND GATES
D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC SN54HC10 . . . J OR W PAC.SNJ54HC10J - TRIPLE 3-INPUT POSITIVE-NAND GATES
D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC SN54HC10 . . . J OR W PAC.SNJ54HC109W - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
D Wide Operating Voltage Range of 2 V to 6 V D Low Input Current of 1 µA Max D High-Current Outputs Drive Up To 10 LSTTL Loads SN54HC109 . . . J OR W .SNJ54HC109FK - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
D Wide Operating Voltage Range of 2 V to 6 V D Low Input Current of 1 µA Max D High-Current Outputs Drive Up To 10 LSTTL Loads SN54HC109 . . . J OR W .M54HC109 - Rad-hard high speed 2V to 6V CMOS logic
Product status link M54HCxxx, M54HCTxxx M54HCxxx, M54HCTxxx Datasheet Rad-hard high speed 2 to 6 V CMOS logic series Features • ESCC qualified • 7 V .CD54HC10F - Triple 3-Input NAND Gates
CD74HC10, CD54HC10 SCHS128D – AUGUST 1997 – REVISED JULY 2021 CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltag.