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74LS74 Datasheet, Features, Application

74LS74 LOW-POWER SCHOTTKY

SN74LS74A Dual D-Type Positive Edge-Triggered Flip.

Motorola
rating-1 30

74LS74 - DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce.
Fairchild Semiconductor
rating-1 16

DM74LS74A - Dual Positive-Edge-Triggered D Flip-Flops

DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS74A Dual Posit.
Texas Instruments
rating-1 10

74LS74 - Dual D-Type Positive-Edge-Triggered Flip-Flop

SN5474, SN54LS74A, SN54S74 SN7474. SN74LS74A, SN74S74 DUAL DĆTYPE POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH PRESET AND CLEAR SDLS119 − DECEMBER 1983 − R.
Texas Instruments
rating-1 8

74LS74A - Dual D-Type Positive-Edge-Triggered Flip-Flop

SN5474, SN54LS74A, SN54S74 SN7474. SN74LS74A, SN74S74 DUAL DĆTYPE POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH PRESET AND CLEAR SDLS119 − DECEMBER 1983 − R.
National Semiconductor
rating-1 7

DM74LS74A - Dual Positive-Edge-Triggered D Flip-Flops

54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS74 DM54LS74A DM74LS74.
Hitachi Semiconductor
rating-1 6

74LS74 - Dual D-type Positive Edge-triggered Flip-Flops

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.
ON Semiconductor
rating-1 5

74LS74 - LOW-POWER SCHOTTKY

SN74LS74A Dual D-Type Positive Edge-Triggered Flip-Flop The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high sp.
Fairchild Semiconductor
rating-1 4

74LS74 - Dual Positive-Edge-Triggered D Flip-Flops

DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS74A Dual Posit.
Motorola
rating-1 4

SN74LS748 - 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS

10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decodi.
Renesas
rating-1 4

HD74LS74A - Dual D-type Positive Edge-triggered Flip-Flops

Preliminary Datasheet HD74LS74A Dual D-type Positive Edge-triggered Flip-Flops (with Preset and Clear) R04DS0012EJ0400 (Previous: REJ03D0415-0300) R.
Renesas
rating-1 4

HD74LS74AP - Dual D-type Positive Edge-triggered Flip-Flops

Preliminary Datasheet HD74LS74A Dual D-type Positive Edge-triggered Flip-Flops (with Preset and Clear) R04DS0012EJ0400 (Previous: REJ03D0415-0300) R.
ETC
rating-1 3

SK74LS74A - INTEGRATED CIRCUIT PINOUTS

.
National Semiconductor
rating-1 3

74LS74 - Dual Positive-Edge-Triggered D Flip-Flops

54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS74 DM54LS74A DM74LS74.
ON Semiconductor
rating-1 3

SN74LS74A - Dual D-Type Positive Edge-Triggered Flip-Flop

SN74LS74A Dual D−Type Positive Edge−Triggered Flip−Flop The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high sp.
NTE
rating-1 3

NTE74LS74A - Dual D-Type Positive-Edge-Triggered Flip-Flop

NTE74LS74A Integrated Circuit TTL, Dual D−Type Positive−Edge−Triggered Flip−Flop w/Preset and Clear Description: The NTE74LS74A contains two independ.
Hitachi Semiconductor
rating-1 2

HD74LS74A - Dual D-type Positive Edge-triggered Flip-Flops

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.
Motorola
rating-1 1

SN74LS74A - DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D.
Texas Instruments
rating-1 1

SN74LS74A - Dual D-Type Positive-Edge Triggered Flip-Flops

SN5474, SN54LS74A, SN54S74 SN7474. SN74LS74A, SN74S74 DUAL DĆTYPE POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH PRESET AND CLEAR SDLS119 − DECEMBER 1983 − R.
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