BT168 Datasheet | Specifications & PDF Download

Philips Semiconductors Product specification Thyristors logic level for RCD/ GFI/ LCCB applications GENERAL DESCRIPTION Glass passivated, sensitive

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BT168G SCR 21 August 2018 Product data sheet 1. General description Planar passivated Silicon Controlled Rectifier with sensitive gate in a SOT54 (T

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SOT223 BT168GW SCR 17 March 2014 Product data sheet 1. General description Planar passivated SCR with sensitive gate in a SOT223 surface mountable

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BT168 series Thyristors logic level for RCD/GFI/LCCB applications Rev. 04 — 20 August 2004 Product data sheet 1. Product profile 1.1 General descr

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BT168 series Thyristors logic level for RCD/GFI/LCCB applications Rev. 5 — 1 November 2011 Product data sheet 1. Product profile 1.1 General desc

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BT168E SCR 6 October 2016 Product data sheet 1. General description Planar passivated Silicon Controlled Rectifier with sensitive gate in a SOT54 (T

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SOT223 BT168GWF SCR 11 July 2014 Product data sheet 1. General description Planar passivated SCR with faster switching performance and sensitive ga

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D Members of the Texas Instruments Widebus ™ Family D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D High-Impedanc

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D Members of the Texas Instruments Widebus ™ Family D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D Latch-Up Perf

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INTEGRATED CIRCUITS 74ABT16823A 18-bit bus interface D-type flip-flop with reset and enable (3-State) Product data Replaces data sheet 74ABT16823A/A

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SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS D Members of the Texas Instruments Widebus ™ Family D State-of-the-Art EPIC-ΙΙ

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74ABT16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state Rev. 03 — 16 March 2010 Product data sheet 1. General descriptio

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D Members of Texas Instruments’ Widebus™ Family D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD 17 D Typical VOLP (Output Ground Bounce)

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D Members of Texas Instruments’ Widebus™ Family D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD 17 D Typical VOLP (Output Ground Bounce)

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INTEGRATED CIRCUITS 74ABT16825A 74ABTH16825A 18-bit buffer/line driver; non-inverting (3-State) Product specification Supersedes data of 1995 Jul 14

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INTEGRATED CIRCUITS 74ABT16827A 74ABTH16827A 20-bit buffer/line driver, non-inverting (3-State) Product specification Supersedes data of 1995 Aug 31

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INTEGRATED CIRCUITS 74ABT16821A 74ABTH16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) Product specification Supersedes

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D Members of the Texas Instruments Widebus ™ Family D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D High-Impedanc

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SN54ABT16821, SN74ABT16821 20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS216B – JUNE 1992 – REVISED JANUARY 1997 D Members of the Texas In

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