HC11 Datasheet | Pinout, Features, Price Comparison & PDF

HD74HC114 Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) Description This flip-flop is edge sensitive to the clock input and change

74HC11; 74HCT11 Triple 3-input AND gate Rev. 6 — 19 November 2015 Product data sheet 1. General description The 74HC11; 74HCT11 is a triple 3-input

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC68HC11A8TS/D MC68HC11A8 MC68HC11A1 MC68HC11A0 Technical Summary 8-Bit Microcontroll

www.ti.com SCHS273F – AUGUSTCC19DD977744–HHRCCEV11I11S,,ECCDDDAP55R44IHHL CC20112111 SCHS273F – AUGUST 1997 – REVISED APRIL 2021 CDx4HC11 Triple 3-In

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06

74HC11; 74HCT11 Triple 3-input AND gate Rev. 9 — 21 February 2024 Product data sheet 1. General description The 74HC11; 74HCT11 is a triple 3-input

SN54HC112, SN74HC112 SCLS099H – DECEMBER 1982 – REVISED JUNE 2022 SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 1 Featu

M54HC113 M74HC113 DUAL J-K FLIP FLOP WITH PRESET . . . . . . . . HIGH SPEED fMAX = 71 MHz (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA at TA

74HC112; 74HCT112 Dual JK flip-flop with set and reset; negative-edge trigger Rev. 4 — 11 January 2021 Product data sheet 1. General description T

M74HC11 TRIPLE 3-INPUT AND GATE s s s s s s s HIGH SPEED: tPD = 9ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C HIGH N

MM54HC11 MM74HC11 Triple 3-Input AND Gate January 1988 MM54HC11 MM74HC11 Triple 3-Input AND Gate General Description These AND gates utilize advance

MC74HC112A Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS The MC74HC112A is identical in pinout to the LS112. The device in

74HC112; 74HCT112 Dual JK flip-flop with set and reset; negative-edge trigger Rev. 4 — 11 January 2021 Product data sheet 1. General description T

SN54HC112, SN74HC112 SCLS099H – DECEMBER 1982 – REVISED JUNE 2022 SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 1 Featu

www.ti.com SCHS273F – AUGUSTCC19DD977744–HHRCCEV11I11S,,ECCDDDAP55R44IHHL CC20112111 SCHS273F – AUGUST 1997 – REVISED APRIL 2021 CDx4HC11 Triple 3-In

Product status link M54HCxxx, M54HCTxxx M54HCxxx, M54HCTxxx Datasheet Rad-hard high speed 2 to 6 V CMOS logic series Features • ESCC qualified • 7 V

M54HC112 M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC =

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC68HC11KA4TS/D M68HC11 KA Series Technical Summary 8-Bit Microcontroller 1 Introduct

TC74HC112AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC112AP, TC74HC112AF Dual J-K Flip Flop with Preset and Clear The TC74H