HCT10 Datasheet | Specifications & PDF Download

CHAVES OPTOELETRÔNICAS TRANSMISSIVAS PHCT102/3/4 PHCT202/3/4 VALORES MÁXIMOS ABSOLUTOS(Tamb=25oC) - EMISSOR VR (tensão reversa) IF (corrente direta

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CHAVES OPTOELETRÔNICAS TRANSMISSIVAS PHCT102/3/4 PHCT202/3/4 VALORES MÁXIMOS ABSOLUTOS(Tamb=25oC) - EMISSOR VR (tensão reversa) IF (corrente direta

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74HC107; 74HCT107 Dual JK flip-flop with reset; negative-edge trigger Rev. 7 — 20 February 2024 Product data sheet 1. General description The 74HC

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74HC10-Q100; 74HCT10-Q100 Triple 3-input NAND gate Rev. 2 — 8 January 2021 Product data sheet 1. General description The 74HC10-Q100; 74HCT10-Q100

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74HC107; 74HCT107 Dual JK flip-flop with reset; negative-edge trigger Rev. 7 — 20 February 2024 Product data sheet 1. General description The 74HC

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74HC10; 74HCT10 Triple 3-input NAND gate Rev. 4 — 8 January 2021 Product data sheet 1. General description The 74HC10; 74HCT10 is a triple 3-input N

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CDx4HCT10 Triple 3-Input NAND Gates CD74HCT10, CD54HCT10 SCHS404 – JUNE 2020 1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min)

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CDx4HCT10 Triple 3-Input NAND Gates CD74HCT10, CD54HCT10 SCHS404 – JUNE 2020 1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min)

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74HC109; 74HCT109 Dual JK flip-flop with set and reset; positive-edge-trigger Rev. 5 — 5 August 2021 Product data sheet 1. General description The

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06

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TECHNICAL DATA IN74HCT109A Dual J-K Flip-Flop with set and Reset High-Performance Silicon-Gate CMOS The IN74HCT109A is identical in pinout to the LS/

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www.DataSheet4U.com www.DataSheet4U.com

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74HC107-Q100; 74HCT107-Q100 Dual JK flip-flop with reset; negative-edge trigger Rev. 3 — 7 July 2021 Product data sheet 1. General description The

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CDx4HCT10 Triple 3-Input NAND Gates CD74HCT10, CD54HCT10 SCHS404 – JUNE 2020 1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min)

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Data sheet acquired from Harris Semiconductor SCHS140E March 1998 - Revised October 2003 CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Dual J-K Flip-F

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Data sheet acquired from Harris Semiconductor SCHS139D March 1998 - Revised October 2003 CD54HC107, CD74HC107, CD74HCT107 Dual J-K Flip-Flop with Res

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74HC109; 74HCT109 Dual JK flip-flop with set and reset; positive-edge-trigger Rev. 5 — 5 August 2021 Product data sheet 1. General description The

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CDx4HCT10 Triple 3-Input NAND Gates CD74HCT10, CD54HCT10 SCHS404 – JUNE 2020 1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min)

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M74HCT10 TRIPLE 3-INPUT NAND GATE s HIGH SPEED: tPD = 14ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C COMPATIBLE WITH TTL

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