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• One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA; require...
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• One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx® FPGAs
• Simple interface to the FPGA; requires on...
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• Optimized for 1.8V systems - As fast as 7.1 ns pin-to-pin delays - As low as 14 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD - Optim...
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XCR5128C: 128 Macrocell CPLD with Enhanced Clocking
14*
DS042 (v1.2) August 10, 2000
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Product Specification
Description
Th...
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into them, they require more effective ways of entering data. Most cell phones, for example, use the standard DTMF style keypad and a multi-tap proces...
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Industry's first TotalCMOS™ PLD - both CMOS design and process technologies Fast Zero Power (FZP™) ...
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• Optimized for 1.8V systems - As fast as 7.1 ns pin-to-pin delays - As low as 14 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD - Optim...
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• In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs ♦ Endurance of 20,000 Program/Erase Cycles ♦ Program/Erase Over Full Industrial ...
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