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44 Hits
a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, clear line. T...
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20 Hits
ads included in this Standard are designated by specifying in sequence the nominal pipe size, number of threads per inch, and the thread series symbol...
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15 Hits
◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location
◆ High-speed clock to data access – Commercial: 6/7.5/9/1...
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13 Hits
• Equivalent to AMD’s Am29520 bipolar Multilevel Pipeline Register in pinout/function, speed and output drive over full temperature and voltage suppl...
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12 Hits
128K x 36, 256K x 18 memory configurations Supports high system speed: Commercial and Industrial: – 150MHz 3.8ns clock access time – 133MHz 4.2ns cloc...
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12 Hits
◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location
◆ High-speed clock to data access – Commercial: 6.5/7.5/9...
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12 Hits
• Equivalent to AMD’s Am29520 bipolar Multilevel Pipeline Register in pinout/function, speed and output drive over full temperature and voltage suppl...
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12 Hits
x x
x x x
x
True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: ...
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11 Hits
■ Supports bus operation up to 250 MHz ■ Available speed grade is 250 MHz ■ Registered inputs and outputs for pipelined operation ■ 2.5-V core power s...
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11 Hits
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location x High-speed clock to data access
– Commercial: 7.5/9/12n...
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11 Hits
• • • • A, B, C and D speed grades Low input and output leakage ≤1µA (max.) CMOS power levels True TTL input and output compatibility – VOH = 3.3V (t...
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11 Hits
• • • • A, B, C and D speed grades Low input and output leakage ≤1µA (max.) CMOS power levels True TTL input and output compatibility – VOH = 3.3V (t...
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11 Hits
a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, clear line. T...
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11 Hits
parallel inputs, parallel outputs, J-K serial inputs, a SHIFT/LOAD control input, and a direct overriding CLEAR. This shift register can operate in tw...
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11 Hits
• Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst se...
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