The AS7C33128PFD32B and AS7C33128PFD36B are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology.
Features
Organization: 131,072 words × 32 or 36 bits.
Fast clock speeds to 200 MHz.
Fast clock to data access: 3.0/3.5/4.0 ns.
Fast OE access time: 3.0/3.5/4.0 ns.
Fully synchronous register-to-register operation.
Double-cycle deselect.
Asynchronous output enable control.
Available in 100-pin TQFP package www. DataSheet4U. com.
February 2005
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AS7C33128PFD32B AS7C33128PFD36B
3.3V 128K X 32/36 pipeline burst synchronous SRAM
Features
• Organization: 131,072 words × 32 or 36 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Double-cycle deselect • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • • • • • • • Individual byte write and global write Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.
AS7C33128PFD32B Datasheet
