Datasheet4U Logo Datasheet4U.com

AS7C33128PFD36A - (AS7C33128PFD32A / AS7C33128PFD36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM

Download the AS7C33128PFD36A datasheet PDF (AS7C33128PFD32A included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for (as7c33128pfd32a / as7c33128pfd36a) 3.3v 128k x 32/36 pipeline burst synchronous sram.

Description

The AS7C33128PFD32A and AS7C33128PFD36A are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology.

Features

  • Organization: 131,072 words × 32 or 36 bits.
  • Fast clock speeds to 166 MHz in LVTTL/LVCMOS.
  • Fast clock to data access: 3.5/3.8/4.0/5.0 ns.
  • Fast OE access time: 3.5/3.8/4.0/5.0 ns.
  • Fully synchronous register-to-register operation.
  • Single register “Flow-through” mode.
  • Dual-cycle deselect - Single-cycle deselect also available (AS7C33128PFS32A/ www. DataSheet4U. com AS7C33128PFS36A).
  • Pentium®.
  • compatible architecture and timi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AS7C33128PFD32A_AllianceSemiconductorCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AS7C33128PFD36A
Manufacturer Alliance Semiconductor Corporation
File Size 261.10 KB
Description (AS7C33128PFD32A / AS7C33128PFD36A) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
Datasheet download datasheet AS7C33128PFD36A Datasheet
Other Datasheets by Alliance Semiconductor Corporation

Full PDF Text Transcription

Click to expand full text
March 2001 ® AS7C33128PFD32A AS7C33128PFD36A 3.3V 128K × 32/36 pipeline burst synchronous SRAM Features • Organization: 131,072 words × 32 or 36 bits • Fast clock speeds to 166 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.5/3.8/4.0/5.0 ns • Fast OE access time: 3.5/3.8/4.0/5.0 ns • Fully synchronous register-to-register operation • Single register “Flow-through” mode • Dual-cycle deselect - Single-cycle deselect also available (AS7C33128PFS32A/ www.DataSheet4U.com AS7C33128PFS36A) • Pentium®* compatible architecture and timing • Asynchronous output enable control • Economical 100-pin TQFP package • Byte write enables • Multiple chip enables for easy expansion • 3.3 core power supply • 2.5V or 3.
Published: |