AS7C331MFT32A - (AS7C331MFT32A / AS7C331MFT36A) 3.3V 1M x 32/36 Flow-through synchronous SRAM

Description

The AS7C331MFT32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words × 32 or 36 bits.

Fast cycle times of 8.5/10/12 ns with clock access times (tCD) of 7.5/8.5/10 ns.

Three chip enable (CE) inputs permit easy memory expansion.

Features

Organization: 1,048,576 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write.
Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separa.

Alliance Semiconductor Corporation

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Datasheet Details

Part number	AS7C331MFT32A
Manufacturer	Alliance Semiconductor Corporation
File Size	568.20 KB
Description	(AS7C331MFT32A / AS7C331MFT36A) 3.3V 1M x 32/36 Flow-through synchronous SRAM
Datasheet	AS7C331MFT32A Datasheet

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Other Datasheets by Alliance Semiconductor Corporation

AS7C331MFT36A - (AS7C331MFT32A / AS7C331MFT36A) 3.3V 1M x 32/36 Flow-through synchronous SRAM
AS7C331MNTD18A - 3.3V 1M x 18 Pipelined SRAM
AS7C331MNTD32A - (AS7C331MNTD32A / AS7C331MNTD36A) 3.3V 1M x 32/36 Pipelined SRAM
AS7C331MNTD36A - (AS7C331MNTD32A / AS7C331MNTD36A) 3.3V 1M x 32/36 Pipelined SRAM
AS7C33128FT18B - 3.3V 128K x 18 Flow Through Synchronous SRAM
AS7C33128FT32B - (AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
AS7C33128FT36B - (AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
AS7C33128NTD18B - 3.3V 128Kx18 Pipelined SRAM

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December 2004 ® AS7C331MFT32A AS7C331MFT36A 3.3V 1M × 32/36 Flow-through synchronous SRAM Features • • • • • • • Organization: 1,048,576 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write • • • • • • Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs www.DataSheet4U.

Published: Jan 1, 2009 |