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CY2309 - Low Cost 3.3 V Zero Delay Buffer

Download the CY2309 datasheet PDF. This datasheet also covers the CY2305 variant, as both devices belong to the same low cost 3.3 v zero delay buffer family and are provided as variant models within a single manufacturer datasheet.

Description

The CY2309 is a low-cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package.

The CY2305 is an 8-pin version of the CY2309.

It accepts one reference input, and drives out five low skew clocks.

Features

  • 10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies.
  • Zero input-output propagation delay.
  • 60-ps typical cycle-to-cycle jitter (high drive).
  • Multiple low skew outputs.
  • 85 ps typical output-to-output skew.
  • One input drives five outputs (CY2305).
  • One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309).
  • Compatible with Pentium-based systems.
  • Test Mode to bypass phase-locked loop (PLL) (CY2309).
  • Packages:.
  • 8-p.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY2305-Cypress.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY2309C Zero Delay Buffers Cypress Semiconductor
CY2300 Phase-Aligned Clock Multiplier Cypress Semiconductor
CY2302 Frequency Multiplier and Zero Delay Buffer Cypress Semiconductor
CY2303 Phase-Aligned Clock Multiplier Cypress Semiconductor
CY2305C Zero Delay Buffers Cypress Semiconductor

Other Datasheets by Cypress (Infineon)

Part Number Description
CY2304 3.3V Zero Delay Buffer
CY2304NZ Four Output PCI-X and General Purpose Buffer
CY2305 Low Cost 3.3 V Zero Delay Buffer
CY2308 3.3V Zero Delay Buffer
CY23EP05 5 Output Zero Delay Buffer

Full PDF Text Transcription

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CY2305 CY2309 Low Cost 3.3 V Zero Delay Buffer Low Cost 3.3 V Zero Delay Buffer Features ■ 10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies ■ Zero input-output propagation delay ■ 60-ps typical cycle-to-cycle jitter (high drive) ■ Multiple low skew outputs ❐ 85 ps typical output-to-output skew ❐ One input drives five outputs (CY2305) ❐ One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309) ■ Compatible with Pentium-based systems ■ Test Mode to bypass phase-locked loop (PLL) (CY2309) ■ Packages: ❐ 8-pin, 150-mil SOIC package (CY2305) ❐ 16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309) ■ 3.3 V operation ■ Commercial and industrial temperature ranges Functional Description The CY2309 is a low-cost 3.
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