CY2DP3110 buffer equivalent, differential clock/data fanout buffer.
* Ten ECL/PECL differential outputs
* One ECL/PECL differential or single-ended inputs (CLKA)
* One HSTL differential or single-ended inputs (CLKB)
* Hot-.
The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to ac.
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