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CY2DP1504 - 1:4 LVPECL Fanout Buffer

General Description

The CY2DP1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications.

The CY2DP1504 can select between two separate LVPECL input clock pairs using the IN_SEL pin.

Key Features

  • Functional.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY2DP1504 1:4 LVPECL Fanout Buffer with Selectable Clock Input Features ■ ■ ■ ■ ■ ■ ■ ■ ■ Functional Description The CY2DP1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1504 can select between two separate LVPECL input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.