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CY2DP818 - 1:8 Clock Fanout Buffer

General Description

The Cypress CY2DP818 fanout buffer

Key Features

  • Low-voltage operation VDD = 3.3 V.
  • 1:8 fanout.
  • Operation to350 MHz.
  • Single input configurable for LVDS, LVPECL, or LVTTL.
  • 8 pair of LVPECL outputs.
  • Drives a 50 ohm load.
  • Low input capacitance.
  • Low output skew.
  • Low propagation delay (tpd = 4 ns, typical).
  • Industrial temperature range.
  • 38-pin TSSOP Package Logic Block Diagram INPUT (LVPECL / LVDS / LVTTL) INPUT A INPUT B InConfig.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY2DP818 1:8 Clock Fanout Buffer 1:8 Clock Fanout Buffer Features ■ Low-voltage operation VDD = 3.3 V ■ 1:8 fanout ■ Operation to350 MHz ■ Single input configurable for LVDS, LVPECL, or LVTTL ■ 8 pair of LVPECL outputs ■ Drives a 50 ohm load ■ Low input capacitance ■ Low output skew ■ Low propagation delay (tpd = 4 ns, typical) ■ Industrial temperature range ■ 38-pin TSSOP Package Logic Block Diagram INPUT (LVPECL / LVDS / LVTTL) INPUT A INPUT B InConfig Description The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs. Designed for data-communications clock management applications, the large fanout from a single input reduces loading on the input clock.