CY2DP3120 Description
The CY2DP3120 is a low-skew, low propagation delay 1-to-20 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz.
CY2DP3120 Key Features
- Twenty ECL/PECL differential outputs
- One ECL/PECL patible differential or single-ended clock inputs
- One HSTL patible differential or single-ended clock inputs
- Hot-swappable/-insertable
- 50 ps output-to-output skew
- 150 ps device-to-device skew
- 500 ps propagation delay (typical)
- 1.4 ps RMS period jitter (max.)
- 1.5 GHz Operation (2.7 GHz max. toggle frequency)
- PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V