CY2DP3110 Overview
The CY2DP3110 is a low-skew, low propagation delay 2-to-10 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz.
CY2DP3110 Key Features
- Ten ECL/PECL differential outputs
- One ECL/PECL differential or single-ended inputs (CLKA)
- One HSTL differential or single-ended inputs (CLKB)
- Hot-swappable/-insertable
- 50 ps output-to-output skew
- 150 ps device-to-device skew
- 400 ps propagation delay (typical)
- 1.2 ps RMS period jitter (max.)
- 1.5 GHz Operation (2.7 GHz maximum toggle frequency)
- PECL and HSTL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V