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CY7C1041CV33 - 256K x 16 Static RAM

Download the CY7C1041CV33 datasheet PDF. This datasheet also covers the CY7 variant, as both devices belong to the same 256k x 16 static ram family and are provided as variant models within a single manufacturer datasheet.

General Description

of Read and Write modes.

I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW).

Key Features

  • Pin equivalent to CY7C1041BV33.
  • High speed.
  • tAA = 10 ns.
  • Low active power.
  • 324 mW (max. ).
  • 2.0V data retention.
  • Automatic power-down when deselected.
  • TTL-compatible inputs and outputs.
  • Easy memory expansion with CE and OE features HIGH Enable (BHE) is LOW, then data from I/O pins (I/O8.
  • I/O15) is written into the location specified on the address pins (A0.
  • A17). Reading from the device is accomplished.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7-C1041CV.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1041 256K x 16 Static RAM
CY7C1041B 256K x 16 Static RAM
CY7C1041BN 256K x 16 Static RAM
CY7C1041BV33 256K x 16 Static RAM
CY7C1041D 4-Mbit (256K x 16) Static RAM
CY7C1041DV33 4-Mbit (256K x 16) Static RAM
CY7C1041V33 256K x 16 Static RAM
CY7C1046D 4-Mbit (1 M x 4) Static RAM
CY7C1046DV33 4-Mbit (1 M x 4) Static RAM
CY7C1049 512K x 8 Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1041CV33 256K x 16 Static RAM Features • Pin equivalent to CY7C1041BV33 • High speed — tAA = 10 ns • Low active power — 324 mW (max.) • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features HIGH Enable (BHE) is LOW, then data from I/O pins (I/O8–I/O15) is written into the location specified on the address pins (A0–A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15.