CY7 Datasheet | Specifications & PDF Download

USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C344B 32-Macrocell MAX® EPLD Features • High-performance, high-density replacement for TTL, 74HC, and custom

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1CY 7C42 65 fax id: 5413 PRELIMINARY CY7C4255 CY7C4265 8K/16Kx18 Deep Sync FIFOs Features • High-speed, low-power, first-in first-out (FIFO) memor

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1CY7C274 CY7C271 CY7C274 32K x 8 Power Switched and Reprogrammable PROM Features • CMOS for optimum speed/power • Windowed for reprogrammability • H

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36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

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CY7C4261V CY7C4281V/CY7C4291V 16K/64K/128K × 9 Low-Voltage Deep Sync™ FIFOs 16K/64K/128K × 9 Low-Voltage Deep Sync™ FIFOs Features ■ 3.3 V operation

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1-Mbit (128 K × 8) Static RAM Features ■ Temperature Ranges ❐ Industrial: –40 °C to 85 °C ❐ Automotive-A: –40 °C to 85 °C ■ Pin and Function compatibl

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1CY7C266 CY7C266 8Kx8 Power-Switched and Reprogrammable PROM Features • CMOS for optimum speed/power • Windowed for reprogrammability • High speed —

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CY7C1305BV18 CY7C1307BV18 18-Mbit Burst of 4 Pipelined SRAM with QDR™ Architecture Features Functional Description • Separate independent Read and

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www.DataSheet4U.com 50 CY7C150 1Kx4 Static RAM Features • Memory reset function • 1024 x 4 static RAM for control store in high-speed computers • CM

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fax id: 61071CY7C342B CY7C342B Features • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array

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CY7C4281 CY7C4291 64K/128K x 9 Deep Sync FIFOs Features • High-speed, low-power, first-in first-out (FIFO) memories • 64K × 9 (CY7C4281) • 128K × 9

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CY7C4221 CY7C42311 K / 2 K × 9 Synchronous FIFOs CY7C4221 / CY7C4231 1 K / 2 K × 9 Synchronous FIFOs 1 K / 2 K × 9 Synchronous FIFOs Features ■ High

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CY7C1521KV18 72-Mbit DDR II SRAM Four-Word Burst Architecture 72-Mbit DDR II SRAM Four-Word Burst Architecture Features ■ 72-Mbit Density (2M × 36) ■

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82A CY7C281A CY7C282A 1K x 8 PROM Features • CMOS for optimum speed/power • High speed — 25 ns (commercial) — 30 ns (military) • Low power — 495 mW

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CY7C9689 TAXI™ Compatible HOTLink® Transceiver Features Second-generation HOTLink® technology AMD™ AM7968/7969 TAXIchip™ compatible 8-bit 4B/5B or 10

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1CY 7C33 5 fax id: 6018 CY7C335 www.DataSheet4U.com Universal Synchronous EPLD Features • 100-MHz output registered operation • Twelve I/O macrocel

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CY7C1034DV33 6-Mbit (256K X 24) Static RAM Features ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 175 mA at f = 100 MHz ■ Low CMOS standby po

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www.DataSheet4U.com CY7C0430BV CY7C0430CV 10 Gb/s 3.3V QuadPort™ DSE Family Features • QuadPort™ datapath switching element (DSE) family allows four

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CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features • 18-Mbit density (2M x 8, 2M x 9, 1M x 18

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