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CY7C1302DV25 - 9-Mbit Burst of Two Pipelined SRAMs

CY7C1302DV25 Description

www.DataSheet4U.com PREMILINARY CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture .
The CY7C1302DV25 is a 2.

CY7C1302DV25 Features

* Separate independent Read and Write data ports
* Supports concurrent transactions
* 167-MHz clock for high bandwidth
* 2.5 ns clock-to-Valid access time
* 2-word burst on all accesses
* Double Data Rate (DDR) interfaces on both Read and Write ports (

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Datasheet Details

Part number
CY7C1302DV25
Manufacturer
Cypress Semiconductor
File Size
245.82 KB
Datasheet
CY7C1302DV25_CypressSemiconductor.pdf
Description
9-Mbit Burst of Two Pipelined SRAMs

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9-Mbit Burst Two Pipelined SRAMs Cypress Semiconductor
Cypress Semiconductor CY7C1302DV25-like datasheet