CY7C1371C Datasheet (Cypress) - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture

CY7C1371C, 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture

1] The CY7C1371C/CY7C1373C is a 3.3V, 512K x 36/ 1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

The CY7C1371C/ CY7C1373C is equipped with the advanced No Bus Latency™ (NoBL™) logic r

CY7C1371C Features

* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

* Can support up to 133-MHz bus operations with zero wait states

* Data is transferred on every clock

* Pin compatible and functionally equivalent to ZBT™ devices

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