CY7C1371C

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture

Cypress

CY7C1371C Features

* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

* Can support up to 133-MHz bus operations with zero wait states

* Data is transferred on every clock

* Pin compatible and functionally equivalent to ZBT™ devices

* Int

CY7C1371C General Description

1] The CY7C1371C/CY7C1373C is a 3.3V, 512K x 36/ 1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371C/ CY7C1373C is equipped with the advanced No Bus Latency™ (NoBL™) logic r.

CY7C1371C Datasheet (791.68 KB)

CY7C1371C Datasheet Preview — Preview of CY7C1371C PDF

Datasheet Details

Part number:

CY7C1371C

Manufacturer:

Cypress

File Size:

791.68 KB

Description:

18-mbit (512k x 36/1m x 18) flow-through sram with nobl architecture.

📁 Related Datasheet

CY7C1371B (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM (Cypress Semiconductor)

CY7C1371D 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM (Cypress Semiconductor)

CY7C1371DV25 (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM (Cypress Semiconductor)

CY7C1371KV33 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM (Cypress Semiconductor)

CY7C1371KVE33 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM (Cypress Semiconductor)

CY7C1371S 18-Mbit (512K x 36) Flow-Through SRAM (Cypress)

CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM (Cypress Semiconductor)

CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)

CY7C1370CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)

CY7C1370D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)

TAGS

CY7C1371C 18-Mbit 512K Flow-Through SRAM with NoBL Architecture Cypress

Image Gallery

CY7C1371C Features

CY7C1371C General Description

Datasheet Details

File Size:

Description:

CY7C1371C Distributor