* No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
* Supports up to 133-MHz bus operations with zero wait states
* Data is transferred on every clock
* Pin-compatible and functionally equivalent to ZBT™ devices
* Internally self-timed outp
CY7C1371D Datasheet (802.19 KB)
CY7C1371D
Cypress Semiconductor
802.19 KB
18-mbit (512 k x 36/1 m x 18) flow-through sram.
CY7C1371D CY7C1373D
18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL.
📁 Related Datasheet
CY7C1371B (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM (Cypress Semiconductor)
CY7C1371C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
CY7C1371DV25 (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM (Cypress Semiconductor)
CY7C1371KV33 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM (Cypress Semiconductor)
CY7C1371KVE33 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM (Cypress Semiconductor)
CY7C1371S 18-Mbit (512K x 36) Flow-Through SRAM (Cypress)
CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM (Cypress Semiconductor)
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
