* Pin-compatible and functionally equivalent to ZBT™
* Supports 250-MHz bus operations with zero wait states
* Available speed grades are 250, 200, and 167 MHz
* Internally self-timed output buffer control to eliminate the need to use asynchronous OE
* Fully registered (inputs an
CY7C1370D Datasheet (734.23 KB)
CY7C1370D
Cypress
734.23 KB
18-mbit (512 k 횞 36/1 m 횞 18) pipelined sram.
CY7C1370D CY7C1372D
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Arch.
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