CY7C1371B - (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM

Product Overview

Cypress Semiconductor

Datasheet Details

Part number	CY7C1371B
Manufacturer	Cypress Semiconductor
File Size	932.55 KB
Description	(CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM
Datasheet	CY7C1371B Datasheet
Additional preview pages of the CY7C1371B datasheet.

Product details

Description

The CY7C1371B/CY7C1373B is 3.3V, 512K × 36 and 1M × 18 synchronous flow-thru burst SRAMs, respectively designed to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Features

Pin compatible and functionally equivalent to ZBT devices.
Supports 117-MHz bus operations with zero wait states.
Data is transferred on every clock.
Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
Registered inputs for flow-thru operation.
Byte Write capability.
Common I/O architecture.
Fast clock-to-output times.
7.5 ns (for 117-MHz device).
8.5 ns (for 100-MHz.

📁 Similar Datasheet

CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
CY7C1371S - 18-Mbit (512K x 36) Flow-Through SRAM (Cypress)
CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
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CY7C1372CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1372D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)

Other Datasheets by Cypress Semiconductor

CY7C1371D - 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
CY7C1371DV25 - (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM
CY7C1371KV33 - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1371KVE33 - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1370B - (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM
CY7C1370DV25 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Published: Jan 25, 2010 |