* Pin-compatible and functionally equivalent to ZBT™
* Supports 250-MHz bus operations with zero wait states
* Available speed grades are 250, 200, and 167 MHz
* Internally self-timed output buffer control to eliminate the need to use asynchronous OE
* Fully registered (inputs an
CY7C1372D Datasheet (734.23 KB)
CY7C1372D
Cypress
734.23 KB
18-mbit (512 k 횞 36/1 m 횞 18) pipelined sram.
CY7C1370D CY7C1372D
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Arch.
📁 Related Datasheet
CY7C1372B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM (Cypress Semiconductor)
CY7C1372C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1372DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM (Cypress Semiconductor)
CY7C1372KV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM (Cypress Semiconductor)
CY7C1372KV33 18-Mbit (512K x 36/1M x 18) Pipelined SRAM (Cypress Semiconductor)
CY7C1372KVE33 18-Mbit (512K x 36/1M x 18) Pipelined SRAM (Cypress Semiconductor)
CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM (Cypress Semiconductor)
CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
