* Pin-compatible and functionally equivalent to ZBT™
* Supports 200-MHz bus operations with zero wait states
* Available speed grades are 200 and 167 MHz
* Internally self-timed output buffer control to eliminate the need to use asynchronous OE
* Fully registered (inputs and outp
CY7C1372DV25 Datasheet (625.09 KB)
CY7C1372DV25
Cypress Semiconductor
625.09 KB
18-mbit (512k x 36/1m x 18) pipelined sram.
CY7C1370DV25 CY7C1372DV25
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Ar.
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