CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture

Product Overview

Cypress

Part number	CY7C1370CV25
Manufacturer	Cypress
File Size	712.71 KB
Description	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
Datasheet	CY7C1370CV25 Datasheet
Additional preview pages of the CY7C1370CV25 datasheet.

The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively.

Pin-compatible and functionally equivalent to ZBT™.
Supports 250-MHz bus operations with zero wait states.
Available speed grades are 250, 225, 200 and 167 MHz.
Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
Fully registered (inputs and outputs) for pipelined operation.
Byte Write capability.
Single 2.5V power supply.
Fast clock-to-output times.
2.6 ns (for 250-MHz device).

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Other Datasheets by Cypress

CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture

Published: Aug 19, 2005 |