Datasheet4U Logo Datasheet4U.com

CY7C1370B Datasheet - Cypress Semiconductor

CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

The CY7C1370B and CY7C1372B SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieve Zero Bus Latency. They integrate 524,288 × 36 and 1,048,576 × 18 SRAM cells, respectively, with advanced sy.

CY7C1370B Features

* Zero Bus Latency, no dead cycles between Write and Read cycles

* Fast clock speed: 200, 167, 150, and 133 MHz

* Fast access time: 3.0, 3.4, 3.8, and 4.2 ns

* Internally synchronized registered outputs eliminate the need to control OE

* Single 3.3V

* 5

CY7C1370B_CypressSemiconductor.pdf

Preview of CY7C1370B PDF
CY7C1370B Datasheet Preview Page 2 CY7C1370B Datasheet Preview Page 3

Datasheet Details

Part number:

CY7C1370B

Manufacturer:

Cypress Semiconductor

File Size:

811.36 KB

Description:

(cy7c1370b / cy7c1372b) 512k x 36/1m x 18 pipelined sram.

📁 Related Datasheet

CY7C1370C 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)

CY7C1370CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)

CY7C1370D 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)

CY7C1370DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM (Cypress Semiconductor)

CY7C1370KV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM (Cypress Semiconductor)

CY7C1370KV33 18-Mbit (512K x 36/1M x 18) Pipelined SRAM (Cypress Semiconductor)

CY7C1370KVE33 18-Mbit (512K x 36/1M x 18) Pipelined SRAM (Cypress Semiconductor)

CY7C1371B (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM (Cypress Semiconductor)

TAGS

CY7C1370B CY7C1370B CY7C1370B CY7C1372B 512K Pipelined SRAM Cypress Semiconductor

CY7C1370B Distributor