Datasheet4U Logo Datasheet4U.com

CY7C1370B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

CY7C1370B Description

CY7C1370B CY7C1372B 512K × 36/1M × 18 Pipelined SRAM with NoBL Architecture .
The CY7C1370B and CY7C1372B SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa.

CY7C1370B Features

* Zero Bus Latency, no dead cycles between Write and Read cycles
* Fast clock speed: 200, 167, 150, and 133 MHz
* Fast access time: 3.0, 3.4, 3.8, and 4.2 ns
* Internally synchronized registered outputs eliminate the need to control OE
* Single 3.3V
* 5

CY7C1370B Applications

* Interleaved or linear four-word burst capability
* Individual byte Write (BWSa
* BWSd) control (may be tied LOW)
* CEN pin to enable clock and suspend operations
* Three chip enables for simple depth expansion
* JTAG boundary scan (BGA package only)

📥 Download Datasheet

Preview of CY7C1370B PDF
datasheet Preview Page 2 datasheet Preview Page 3

Datasheet Details

Part number
CY7C1370B
Manufacturer
Cypress Semiconductor
File Size
811.36 KB
Datasheet
CY7C1370B_CypressSemiconductor.pdf
Description
(CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

📁 Related Datasheet

  • CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
  • CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
  • CY7C1371S - 18-Mbit (512K x 36) Flow-Through SRAM (Cypress)
  • CY7C1372C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1372CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1372D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)

📌 All Tags

CY7C1370B CY7C1372B 512K Pipelined SRAM Cypress Semiconductor
Cypress Semiconductor CY7C1370B-like datasheet