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CY7C1370B

(CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

CY7C1370B Features

* Zero Bus Latency, no dead cycles between Write and Read cycles

* Fast clock speed: 200, 167, 150, and 133 MHz

* Fast access time: 3.0, 3.4, 3.8, and 4.2 ns

* Internally synchronized registered outputs eliminate the need to control OE

* Single 3.3V

* 5

CY7C1370B General Description

The CY7C1370B and CY7C1372B SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieve Zero Bus Latency. They integrate 524,288 × 36 and 1,048,576 × 18 SRAM cells, respectively, with advanced sy.

CY7C1370B Datasheet (811.36 KB)

Preview of CY7C1370B PDF

Datasheet Details

Part number:

CY7C1370B

Manufacturer:

Cypress Semiconductor

File Size:

811.36 KB

Description:

(cy7c1370b / cy7c1372b) 512k x 36/1m x 18 pipelined sram.

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TAGS

CY7C1370B CY7C1370B CY7C1372B 512K Pipelined SRAM Cypress Semiconductor

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