CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture

Product Overview

Cypress

Part number	CY7C1370C
Manufacturer	Cypress
File Size	704.25 KB
Description	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
Datasheet	CY7C1370C Datasheet
Additional preview pages of the CY7C1370C datasheet.

The CY7C1370C and CY7C1372C are 3.3V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively.

Pin-compatible and functionally equivalent to ZBT™.
Supports 250-MHz bus operations with zero wait states.
Available speed grades are 250, 225, 200 and 167 MHz.
Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
Fully registered (inputs and outputs) for pipelined operation.
Byte Write capability.
Single 3.3V power supply.
3.3V/2.5V I/O power supply.
Fast clock-to-output times.

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CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
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Published: Aug 19, 2005 |