CY7C1370C Datasheet - Cypress

CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture

The CY7C1370C and CY7C1372C are 3.3V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively.

They are designed to support unlimited true back-to-back Read/Write operations with no wait states.

The CY7C1370C and CY7C1372C are equipped with the advanc

CY7C1370C Features

* Pin-compatible and functionally equivalent to ZBT™

* Supports 250-MHz bus operations with zero wait states

* Available speed grades are 250, 225, 200 and 167 MHz

* Internally self-timed output buffer control to eliminate the need to use asynchronous OE

* Ful

Datasheet Details

CY7C1370C

Cypress

704.25 KB

512k x 36/1m x 18 pipelined sram with nobl architecture.

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