CY7C1371DV25 Features
* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
* Can support up to 133-MHz bus operations with zero wait states
* Data is transferred on every clock
* Pin compatible and functionally equivalent to ZBT™ devices
* Int
CY7C1373DV25_CypressSemiconductor.pdf
Datasheet Details
CY7C1371DV25, CY7C1373DV25
Cypress Semiconductor
486.89 KB
(cy7c1371dv25 / cy7c1373dv25) flow-through sram.
This datasheet PDF includes multiple part numbers: CY7C1371DV25, CY7C1373DV25.
Please refer to the document for exact specifications by model.
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CY7C1371DV25 Distributor
