* No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
* Supports up to 133-MHz bus operations with zero wait states
* Data is transferred on every clock
* Pin-compatible and functionally equivalent to ZBT™ devices
* Internally self-timed outp
CY7C1371KV33 Datasheet (0.96 MB)
CY7C1371KV33
Cypress Semiconductor
0.96 MB
18-mbit (512k x 36/1m x 18) flow-through sram.
CY7C1371KV33 CY7C1371KVE33
CY7C1373KV33
18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC)
18-Mbit (512K × 36/1M × 18) .
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