CY7C1371S Datasheet (Cypress) - 18-Mbit (512K x 36) Flow-Through SRAM

CY7C1371S, 18-Mbit (512K x 36) Flow-Through SRAM

The CY7C1371S is a 3.3 V, 512K × 36 Synchronous flow through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations with no wait state insertion.

The CY7C1371S is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write o

CY7C1371S Features

* No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles

* Supports up to 133-MHz bus operations with zero wait states

* Data is transferred on every clock

* Pin-compatible and functionally equivalent to ZBT™ devices

* Internally self-timed outp