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CY7C1371S 18-Mbit (512K x 36) Flow-Through SRAM

CY7C1371S Description

CY7C1371S 18-Mbit (512K × 36) Flow-Through SRAM with NoBL™ Architecture 18-Mbit (512K × 36) Flow-Through SRAM with NoBL™ Architecture .
The CY7C1371S is a 3.

CY7C1371S Features

* No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
* Supports up to 133-MHz bus operations with zero wait states
* Data is transferred on every clock
* Pin-compatible and functionally equivalent to ZBT™ devices
* Internally self-timed outp

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Datasheet Details

Part number
CY7C1371S
Manufacturer
Cypress
File Size
625.63 KB
Datasheet
CY7C1371S-Cypress.pdf
Description
18-Mbit (512K x 36) Flow-Through SRAM

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18-Mbit 512K Flow-Through SRAM Cypress
Cypress CY7C1371S-like datasheet