CY7C1371S

18-Mbit (512K x 36) Flow-Through SRAM

Cypress

CY7C1371S Features

* No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles

* Supports up to 133-MHz bus operations with zero wait states

* Data is transferred on every clock

* Pin-compatible and functionally equivalent to ZBT™ devices

* Internally self-timed outp

CY7C1371S General Description

The CY7C1371S is a 3.3 V, 512K × 36 Synchronous flow through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations with no wait state insertion. The CY7C1371S is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write o.

CY7C1371S Datasheet (625.63 KB)

CY7C1371S Datasheet Preview — Preview of CY7C1371S PDF

Datasheet Details

Part number:

CY7C1371S

Manufacturer:

Cypress

File Size:

625.63 KB

Description:

18-mbit (512k x 36) flow-through sram.

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TAGS

CY7C1371S 18-Mbit 512K Flow-Through SRAM Cypress

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CY7C1371S Features

CY7C1371S General Description

Datasheet Details

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CY7C1371S Distributor