Description
CY7C1370B CY7C1372B 512K × 36/1M × 18 Pipelined SRAM with NoBL Architecture .
The CY7C1370B and CY7C1372B SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa.
Features
* Zero Bus Latency, no dead cycles between Write and Read cycles
* Fast clock speed: 200, 167, 150, and 133 MHz
* Fast access time: 3.0, 3.4, 3.8, and 4.2 ns
* Internally synchronized registered outputs eliminate the need to control OE
* Single 3.3V
* 5
Applications
* Interleaved or linear four-word burst capability
* Individual byte Write (BWSa
* BWSd) control (may be tied LOW)
* CEN pin to enable clock and suspend operations
* Three chip enables for simple depth expansion
* JTAG boundary scan (BGA package only)
