CY7C1372B
Cypress Semiconductor
811.36kb
(cy7c1370b / cy7c1372b) 512k x 36/1m x 18 pipelined sram. The CY7C1370B and CY7C1372B SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa. These SRAM
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CY7C1372C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
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CY7C1370C CY7C1372C
512K x 36/1M x 18 Pipelined SRAM with NoBL™ Architecture
Features
• Pin-patible and functionally equivalent to ZBT™ • Supports.
CY7C1372CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
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CY7C1370CV25 CY7C1372CV25
512K x 36/1M x 18 Pipelined SRAM with NoBL™ Architecture
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• Pin-patible and functionally equivalent to ZBT™ • Su.
CY7C1372D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
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18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture
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CY7C1372DV25 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
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CY7C1372KV25 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
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18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Ar.
CY7C1372KV33 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
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CY7C1372KVE33 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
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CY7C1370B - (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM
(Cypress Semiconductor)
CY7C1370B CY7C1372B
512K × 36/1M × 18 Pipelined SRAM with NoBL Architecture
Features
• Zero Bus Latency, no dead cycles between Write and Read cycle.
CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
(Cypress)
CY7C1370C CY7C1372C
512K x 36/1M x 18 Pipelined SRAM with NoBL™ Architecture
Features
• Pin-patible and functionally equivalent to ZBT™ • Supports.
CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
(Cypress)
CY7C1370CV25 CY7C1372CV25
512K x 36/1M x 18 Pipelined SRAM with NoBL™ Architecture
Features
• Pin-patible and functionally equivalent to ZBT™ • Su.
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