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CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM

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Description

CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture .

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Datasheet Specifications

Part number
CY7C1303BV25
Manufacturer
Cypress Semiconductor
File Size
969.86 KB
Datasheet
CY7C1303BV25-CypressSemiconductor.pdf
Description
18-Mbit Burst of Two-Pipelined SRAM

Features

* Separate independent read and write data ports
* Supports concurrent transactions
* 167 MHz clock for high bandwidth
* 2.5 ns clock-to-valid access time
* Two word burst on all accesses
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 33

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