CY7C1303BV25 Datasheet - Cypress Semiconductor

CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM

CY7C1303BV25 Features

* Separate independent read and write data ports

* Supports concurrent transactions

* 167 MHz clock for high bandwidth

* 2.5 ns clock-to-valid access time

* Two word burst on all accesses

* Double data rate (DDR) interfaces on both read and write ports (data transferred at 33

Datasheet Details

CY7C1303BV25

Cypress Semiconductor

969.86 KB

18-mbit burst of two-pipelined sram.

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