Datasheet4U Logo Datasheet4U.com

CY7C1304DV25 9-Mbit Burst of 4 Pipelined SRAM

CY7C1304DV25 Description

PRELIMINARY CY7C1304DV25 9-Mbit Burst of 4 Pipelined SRAM with QDR™ Architecture .

CY7C1304DV25 Features

* Separate independent Read and Write data ports
* Supports concurrent transactions
* 167-MHz Clock for high bandwidth
* 2.5 ns Clock-to-Valid access time
* 4-Word Burst for reducing the address bus frequency
* Double Data Rate (DDR) interfaces on bot

📥 Download Datasheet

Preview of CY7C1304DV25 PDF
datasheet Preview Page 2 datasheet Preview Page 3

Datasheet Details

Part number
CY7C1304DV25
Manufacturer
Cypress Semiconductor
File Size
222.49 KB
Datasheet
CY7C1304DV25-CypressSemiconductor.pdf
Description
9-Mbit Burst of 4 Pipelined SRAM

📁 Related Datasheet

  • CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C131E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C136AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C136E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
  • CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)

📌 All Tags

9-Mbit Burst Pipelined SRAM Cypress Semiconductor
Cypress Semiconductor CY7C1304DV25-like datasheet