CY7C1304DV25 Datasheet - Cypress Semiconductor

CY7C1304DV25 - 9-Mbit Burst of 4 Pipelined SRAM

CY7C1304DV25 Features

* Separate independent Read and Write data ports

* Supports concurrent transactions

* 167-MHz Clock for high bandwidth

* 2.5 ns Clock-to-Valid access time

* 4-Word Burst for reducing the address bus frequency

* Double Data Rate (DDR) interfaces on bot

Datasheet Details

CY7C1304DV25

Cypress Semiconductor

222.49 KB

9-mbit burst of 4 pipelined sram.

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