CY7C1304DV25 Datasheet - Cypress Semiconductor

CY7C1304DV25 9-Mbit Burst of 4 Pipelined SRAM

CY7C1304DV25 Features

* Separate independent Read and Write data ports

* Supports concurrent transactions

* 167-MHz Clock for high bandwidth

* 2.5 ns Clock-to-Valid access time

* 4-Word Burst for reducing the address bus frequency

* Double Data Rate (DDR) interfaces on bot

Datasheet Details

CY7C1304DV25

Cypress Semiconductor

222.49 KB

9-mbit burst of 4 pipelined sram.

📁 Related Datasheet

CY7C130 1K x 8 Dual-Port Static RAM (Cypress Semiconductor)

CY7C1302CV25 9-Mbit Burst of Two Pipelined SRAMs (Cypress Semiconductor)

CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs (Cypress Semiconductor)

CY7C1303BV18 18-Mbit Burst of 2 Pipelined SRAM (Cypress Semiconductor)

CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM (Cypress Semiconductor)

CY7C1305BV18 18-Mbit Burst of 4 Pipelined SRAM (Cypress Semiconductor)

CY7C1305BV25 18-Mbit Burst of 4 Pipelined SRAM (Cypress Semiconductor)

CY7C1306BV18 18-Mbit Burst of 2 Pipelined SRAM (Cypress Semiconductor)

TAGS

CY7C1304DV25 Distributor