CY7C1302CV25 Datasheet (Cypress Semiconductor) - 9-Mbit Burst of Two Pipelined SRAMs

CY7C1302CV25, 9-Mbit Burst of Two Pipelined SRAMs

The CY7C1302CV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture.

QDR architecture consists of two separate ports to access the memory array.

The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operati

CY7C1302CV25 Features

* Separate independent Read and Write data ports

* Supports concurrent transactions

* 167-MHz clock for high bandwidth

* 2.5 ns clock-to-Valid access time

* 2-word burst on all accesses

* Double Data Rate (DDR) interfaces on both Read and Write ports (