* Separate independent read and write data ports
* Supports concurrent transactions
* 450-MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double data rate (DDR) Interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
CY7C1145KV18 Datasheet (646.01 KB)
CY7C1145KV18
Cypress Semiconductor
646.01 KB
18-mbit qdr ii+ sram four-word burst architecture.
CY7C1143KV18/CY7C1145KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 18-Mbit QDR® II+ SRAM Four-Word Burst Archite.
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