CY7C1145KV18 Datasheet | Cypress

 CY7C1143KV18/CY7C1145KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features - Separate independent read and write data ports - Supports concurrent transactions - 450-MHz clock for high bandwidth - Four-word burst for reducing address bus frequency - Double data rate (DDR) Interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz - Available in 2.0 clock cycle latency - Two input clocks (K and K) for precise DDR timing - SRAM uses rising edges only - Echo clocks (CQ and CQ) simplify data capture in high-speed systems - Data valid pin (QVLD) to indicate valid data on the output - Single multiplexed address input bus latches address inputs for read and write ports - Separate port selects for depth expansion - Synchronous internally self-timed writes - QDR® II+ operates with 2.0 cycle read latency when DOFF is asserted...