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Cypress Semiconductor Electronic Components Datasheet

CY7C1325H Datasheet

4-Mbit Flow-Through Sync SRAM

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CY7C1325H
4-Mbit (256K × 18) Flow-Through
Sync SRAM
4-Mbit (256K × 18) Flow-Through Sync SRAM
Features
256K × 18 common I/O
3.3 V core power supply (VDD)
2.5 V or 3.3 V I/O power supply (VDDQ)
Fast clock-to-output times
6.5 ns (133 MHz version)
Provide high performance 2-1-1-1 access rate
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed write
Asynchronous output enable
Available in Pb-free 100-pin TQFP package
“ZZ” sleep mode option
Functional Description
The CY7C1325H is a 256K × 18 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW[A:B], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
The CY7C1325H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The CY7C1325H operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Logic Block Diagram
A 0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BW B
BW A
BWE
GW
CE 1
CE 2
CE 3
OE
ZZ
ADDRESS
REGISTER
A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQ B,DQP B
WRITE REGISTER
DQ A,DQP A
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
DQ B,DQP B
WRITE DRIVER
DQ A,DQP A
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
INPUT
REGISTERS
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86114 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 23, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1325H Datasheet

4-Mbit Flow-Through Sync SRAM

No Preview Available !

CY7C1325H
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 5
Single Read Accesses ................................................ 5
Single Write Accesses Initiated by ADSP ................... 5
Single Write Accesses Initiated by ADSC ................... 5
Burst Sequences ......................................................... 5
Sleep Mode ................................................................. 5
Interleaved Burst Address Table ................................. 6
Linear Burst Address Table ......................................... 6
ZZ Mode Electrical Characteristics .............................. 6
Truth Table ........................................................................ 7
Truth Table for Read/Write .............................................. 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Neutron Soft Error Immunity ........................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Timing Diagrams ............................................................ 13
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC®Solutions ....................................................... 21
Cypress Developer Community ................................. 21
Technical Support ..................................................... 21
Document Number: 001-86114 Rev. *D
Page 2 of 21


Part Number CY7C1325H
Description 4-Mbit Flow-Through Sync SRAM
Maker Cypress Semiconductor
Total Page 21 Pages
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