Datasheet4U Logo Datasheet4U.com

CY7C1364V25 - 256K x 36/256K x 32/512K x 18 Pipelined SRAM

Download the CY7C1364V25 datasheet PDF (CY7C1360V25 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 256k x 36/256k x 32/512k x 18 pipelined sram.

Description

The CY7C1360V25, CY7C1364V25 and CY7C1362V25 are 2.5V, 256K x 36, 256K x 32 and 512K x 18 synchronous-pipelined cache SRAM, respectively.

They are designed to support zero wait state secondary cache with minimal glue logic.

Features

  • Supports 200-MHz bus.
  • Fully registered inputs and outputs for pipelined operation.
  • Single 2.5V power supply.
  • Fast clock-to-output times.
  • 3.1 ns (for 200-MHz device).
  • 3.5 ns (for 166-MHz device).
  • 4.0 ns (for 133-MHz device.
  • 5.0 ns (for 100-MHz device.
  • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences.
  • Separate processor and controller address strobes.
  • Sy.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1360V25-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

  • CY7C136AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C136E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C131E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
  • CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
  • CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
  • CY7C1371S - 18-Mbit (512K x 36) Flow-Through SRAM (Cypress)
  • CY7C1372C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C136 - 2K x 8 Dual-Port Static RAM
  • CY7C1360C - 9-Mbit Pipelined SRAM
  • CY7C1360V25 - 256K x 36/256K x 32/512K x 18 Pipelined SRAM
  • CY7C1361C - (CY7C1361C / CY7C1363C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
  • CY7C1362C - 9-Mbit Pipelined SRAM
  • CY7C1362V25 - 256K x 36/256K x 32/512K x 18 Pipelined SRAM
  • CY7C1363C - (CY7C1361C / CY7C1363C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
  • CY7C1363D - 9-Mbit Flow-Through SRAM

Full PDF Text Transcription

Click to expand full text
PRELIMINARY CY7C1360V25 CY7C1362V25 CY7C1364V25 256K x 36/256K x 32/512K x 18 Pipelined SRAM Features • Supports 200-MHz bus • Fully registered inputs and outputs for pipelined operation • Single 2.5V power supply • Fast clock-to-output times — 3.1 ns (for 200-MHz device) — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device — 5.0 ns (for 100-MHz device • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Available as a 100-pin TQFP or 119 BGA • “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1360V25, CY7C1364V25 and CY7C1362V25 are 2.
Published: |