Description
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The CY7C1371DV25/CY7C1373DV25 is a 2.5V, 512K x 36/1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.The CY7C1371DV25/CY7C1373DV25 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.This feature dramatically improves the throughput of data through the SRAM, especially in
Features
- No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
- Can support up to 133-MHz bus operations with zero wait states.
- Data is transferred on every clock.
- Pin compatible and functionally equivalent to ZBT™ devices.
- Internally self-timed output buffer control to eliminate the need to use OE.
- Registered inputs for flow-through operation.
- Byte Write capability.
- 2.5V core power supply (VDD).