Datasheet4U Logo Datasheet4U.com

CY7C1371KVE33 - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Download the CY7C1371KVE33 datasheet PDF (CY7C1371KV33 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 18-mbit (512k x 36/1m x 18) flow-through sram.

Features

  • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles.
  • Supports up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin-compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow through operation.
  • Byte write capability.
  • 3.3 V/2.5 V I/O power supply (VDDQ).
  • Fast clock-to-output ti.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1371KV33-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

  • CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
  • CY7C1371S - 18-Mbit (512K x 36) Flow-Through SRAM (Cypress)
  • CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
  • CY7C1372C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1372CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1372D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
  • CY7C1373C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
  • CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C1371KV33 - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
  • CY7C1371B - (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM
  • CY7C1371D - 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
  • CY7C1371DV25 - (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM
  • CY7C1370B - (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM
  • CY7C1370DV25 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
  • CY7C1370KV25 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
  • CY7C1370KV33 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Full PDF Text Transcription

Click to expand full text
CY7C1371KV33 CY7C1371KVE33 CY7C1373KV33 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC) 18-Mbit (512K × 36/1M × 18) Flow-through SRAM with NoBL™ Architecture (With ECC) Features ■ No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin-compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V/2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 6.
Published: |