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CY7C331 Datasheet - Cypress Semiconductor

CY7C331 - Asynchronous Registered EPLD

The CY7C331 is the most versatile PLD available for asynchronous designs. Central resources include twelve full D-type ﬂip-ﬂops with separate set, reset, and clock capability. For increased utility, XOR gates are provided at the D-inputs and the product term allocation per ﬂip-ﬂop is variably distri.

CY7C331 Features

* Twelve I/O macrocells each having:

* One state ﬂip-ﬂop with an XOR sum-of-products input

* One feedback ﬂip-ﬂop with input coming from the I/O pin

* Independent (product term) set, reset, and clock inputs on all registers

* Asynchronous bypass capability on

CY7C331_CypressSemiconductor.pdf