CY7C344B Datasheet PDF - Cypress Semiconductor 32-Macrocell MAX EPLD Specs

CY7C344B - 32-Macrocell MAX EPLD

Datasheet Summary

Description

Available in a 28-pin, 300-mil DIP or windowed J-leaded ceramic chip carrier (HLCC), the CY7C344 represents the Logic Block Diagram [1] 15(22) 15(23) 27(6) 28(7) INPUT INPUT INPUT INPUT INPUT INPUT INPUT 1(8) 13(20) 14(21) INPUT/CLK 2(9) Pin Configurations HLCC Top View I/O I/O I/O VCC GND I/O I/O

Features

High-performance, high-density replacement for TTL, 74HC, and custom logic.
32 macrocells, 64 expander product terms in one LAB.
8 dedicated inputs, 16 I/O pins.
0.8-micron double-metal CMOS EPROM technology.
28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC package densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product ter.

Datasheet Details

Part number	CY7C344B
Manufacturer	Cypress Semiconductor
File Size	241.81 KB
Description	32-Macrocell MAX EPLD
Datasheet	CY7C344B Datasheet
Additional preview pages of the CY7C344B datasheet.

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Full PDF Text Transcription

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USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C344B 32-Macrocell MAX® EPLD Features • High-performance, high-density replacement for TTL, 74HC, and custom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins • 0.8-micron double-metal CMOS EPROM technology • 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC package densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the I/O pins are driven by macrocell registers, there are still 16 “buried” registers available.

Published: Mar 27, 2005 |