CY7C344B Datasheet | Cypress

Features - High-performance, high-density replacement for TTL, 74HC, and custom logic - 32 macrocells, 64 expander product terms in one LAB - 8 dedicated inputs, 16 I/O pins - 0.8-micron double-metal CMOS EPROM technology - 28-pin, 300-mil DIP, cer DIP or 28-pin HLCC, PLCC package densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins municate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the I/O pins are driven by macrocell registers, there are still 16 “buried” registers available. All inputs, macrocells, and I/O pins are interconnected within the LAB. The speed and density of the CY7C344 makes it a natural for all types of applications. With just this one device, the designer can implement plex state machines, registered logic, and binatorial “glue” logic, without using multiple chips. This architectural flexibility allows the CY7C344 to replace multichip TTL solutions, whether they are synchronous, asynchronous, binatorial, or all three. Functional Description Available in a 28-pin, 300-mil DIP or windowed J-leaded ceramic chip carrier (HLCC), the CY7C344 represents the Logic Block Diagram [1] 15(22) 15(23) 27(6) 28(7) INPUT INPUT INPUT INPUT INPUT INPUT INPUT 1(8) 13(20) 14(21) INPUT/CLK 2(9) Pin Configurations HLCC Top View I/O I/O I/O VCC GND I/O I/O 4 3 2 1 28 27 26 I/O INPUT INPUT INPUT INPUT/CLK I/O I/O 5 6 7 8 9 10 11 25 24 23 22 21 20 19 I/O I/O INPUT INPUT INPUT INPUT I/O I/O I/O I O C O N T R O L I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 3(10) 4(11) 5(12) 6(13) 9(16) 10(17) V CC GND I/O I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 I/O I/O 11(18) 12(19) 17(24) 18(25) 19(26) 20(27) 23(2) 24(3) 25(4) 26(5) INPUT INPUT/CLK I/O I/O I/O I/O VCC GND I/O I/O I/O I/O INPUT INPUT I/O INPUT INPUT I/O I/O I/O I/O VCC GND I/O I/O I/O...