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CY7C346 - USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD)

General Description

The CY7C346 is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device.

The MAX® architecture is 100% user-configurable, allowing the device to accommodate a variety of independent logic functions.

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Key Features

  • 128 macrocells in eight logic array blocks (LABs).
  • 20 dedicated inputs, up to 64 bidirectional I/O pins.
  • Programmable interconnect array.
  • 0.8-micron double-metal CMOS EPROM technology.
  • Available in 84-pin CLCC, PLCC, and 100-pin PGA, PQFP The 128 macrocells in the CY7C346 are divided into eight LABs, 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected throug.

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📁 Similar Datasheet

Part Number Description Manufacturer
CY7C340 Multiple Array Matrix High-Density EPLDs Cypress
CY7C342 128-Macrocell MAX EPLDs Cypress
CY7C342B 128-Macrocell MAX EPLDs Cypress
CY7C343 64-Macrocell MAX EPLD Cypress
CY7C343B 64-Macrocell MAX EPLD Cypress

Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C341B 192-Macrocell MAX EPLD
CY7C344 32-Macrocell MAX EPLD
CY7C344B 32-Macrocell MAX EPLD
CY7C331 Asynchronous Registered EPLD
CY7C335 Universal Synchronous EPLD

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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USE ULTRA37000TM FOR ALL NEW DESIGNS CY7C346 128-Macrocell MAX® EPLD Features • 128 macrocells in eight logic array blocks (LABs) • 20 dedicated inputs, up to 64 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology • Available in 84-pin CLCC, PLCC, and 100-pin PGA, PQFP The 128 macrocells in the CY7C346 are divided into eight LABs, 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected through the programmable interconnect array, allowing all signals to be routed throughout the chip.