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EDI

EDI8L32256C Datasheet Preview

EDI8L32256C Datasheet

Static Ram

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EDI8L32256C
256Kx32 SRAM Module
Features
256Kx32 bit CMOS Static
DSP Memory Solution
• Texas Instruments TMS320C3x, TMS320C4x
• Analog SHARCTM DSP
• Motorola DSP96002
Random Access Memory Array
• Fast Access Times: 15, 17, 20 and 25ns
• Individual Byte Enables
• User Configurable Organization
with Minimal Additional Logic
• Master Output Enable and Write Control
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
Surface Mount Package
• 68 Lead PLCC, No. 99, JEDEC MO-47AE
• Small Footprint, 0.990 Sq. In.
• Multiple Ground Pins for Maximum
Noise Immunity
Single +5V (±5%) Supply Operation
Pin Configurations and Block Diagram
256Kx32, 5V Static Ram
The EDI8L32256C is a high speed, 5V, 8 megabit SRAM.
The device is available with access times of 15, 17, 20 and
25ns, allowing the creation of a no wait state DSP memory
solution.
The device can be configured as a 256Kx32 and used to
create a single chip external data memory solution for
Texas Instruments' TMS320C30/31, TMS 320C32 or
TMS320C4x, Motorola's DSP96002 and Analog Device's
SHARCTM DSP.
Alternatively the device's chip enables can be used to
configure it as a 512Kx16. A 512Kx48 program memory
array for Analog's SHARCTM DSP is created using three
devices. If this memory is too deep, two 256Kx24s
(EDI8L24256C) can be used to create a 256Kx48 array or
two 128Kx24s (EDI8L24128C) can be used to create a
128Kx48 array.
The device provides a 32% space savings when compared
to two monolithic 256Kx16, 44 pin SOJs.
The device provides a memory upgrade of the
EDI8L32128C (128Kx32) and the EDI8L3265C (64Kx32).
For more memory the device can be upgraded to the
EDI8L32512C (512Kx32).
NOTE: Solder Reflow temperature should not exceed 260°C for 10 seconds.
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
DQ24
DQ25
DQ26
DQ27
VSS
DQ28
DQ29
DQ30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60 DQ14
59 DQ13
58 DQ12
57 VSS
56 DQ11
55 DQ10
54 DQ9
53 DQ8
52 VCC
51 DQ7
50 DQ6
49 DQ5
48 DQ4
47 VSS
46 DQ3
45 DQ2
44 DQ1
Note: For memory upgrade information refer to page 8, Figure 8 "EDI MCM-L
upgrade path".
Pin Names
AØ-A17
EØ-E1
BSØ-BS3
W
G
DQØ-DQ31
VCC
VSS
NC
AØ-A17
G
W
E1
BSØ
BS1
BS2
BS3
18
Address Inputs
Chip Enables (One per Word)
Byte Selects (One per Byte)
Master Write Enable
Master Output Enable
Common Data Input/Output
Power (+5V±5%)
Ground
No Connection
256Kx32
Memory
Array
DQØ-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
Electronic Designs Incorporated
• One Research Drive • Westborough, MA 01581USA • 508-366-5151 • FAX 508-836-4850 •
http://www.electronic-designs.com
1
EDI8L32256C Rev. 4 3/98 ECO#9662




EDI

EDI8L32256C Datasheet Preview

EDI8L32256C Datasheet

Static Ram

No Preview Available !

Absolute Maximum Ratings*
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Industrial
Storage Temperature
Power Dissipation
Output Current.
Junction Temperature, TJ
-0.5V to 7.0V
0°C to + 70°C
-40°C to +85°C
-55°C to +125°C
3.1 Watts
20 mA
175°C
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions
Parameter
Sym Min Typ Max Units
Supply Voltage VCC 4.75 5.0 5.25 V
Supply Voltage VSS 0 0 0 V
Input High Voltage VIH 2.2 -- VCC+0.5 V
Input Low Voltage VIL -0.3 -- 0.8 V
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
Figure 1
VCC
Figure 2
Q
255
480
30 pF
Q
255
VSS to 3.0V
5ns
1.5V
Figure 1
VCC
480
5 pF
DC Electrical Characteristics
Parameter
Sym
Operating Power Supply Current ICC1
Standby (TTL) Supply Current ICC2
Full StandbySupply Current
ICC3
Input Leakage Current
Output Leakage Current
Output High Volltage
Output Low Voltage
ILI
ILO
VOH
VOL
Conditions
W= VIL, II/O = 0mA,
Min Cycle
E VIH, VIN VIL or
VIN VIH, f=ØMHz
E VCC-0.2V
VIN VCC-0.2V or
VIN 0.2V
VIN = 0V to VCC
V I/O = 0V to VCC
IOH = -4.0mA
IOL = 8.0mA
Min
2.4
Max
15/17
575
120
20
Units
20/25
480 mA
120 mA
20 mA
±10 µA
±10 µA
V
0.4 V
Truth Table
E W G BSØ-3 Mode Output
H X X X Standby High Z
L H H X Output Disable High Z
L X X H Output Disable High Z
L H L L Read DOUT
L L X L Write
DIN
Power
ICC2,ICC3,
ICC1
ICC1
ICC1
ICC1
X Means Don't Care
Capacitance
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Sym
Address Lines
CA
Data Lines
CD/Q
Write & Output Enable Lines W, G
Chip Enable Lines/Byte Select E, BS
Max Unit
20 pF
10 pF
6 pF
9 pF
EDI8L32256C
256Kx32 SRAM Module
2
EDI8L32256C Rev. 4 3/98 ECO#9662


Part Number EDI8L32256C
Description Static Ram
Maker EDI
Total Page 5 Pages
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