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74LS107 Datasheet - ETC

74LS107 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and is not directly related to the transition time of the negat.

74LS107_ETC.pdf

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Datasheet Details

Part number:

74LS107

Manufacturer:

ETC

File Size:

143.69 KB

Description:

Dual negative-edge-triggered master-slave j-k flip-flops.

74LS107 Distributor

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