* Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge
* Double Data Rate interface Differential CLK (/CLK) input Data inputs and DM are synchronized with both edges of DQS Data outputs and DQS are synchronized with a cross po
EDD1208ALTA Datasheet (1.60 MB)
EDD1208ALTA
Elpida Memory
1.60 MB
128 m-bit synchronous dram.
PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2) .
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