* Power supply: VDDQ = 2.5V ± 0.2V : VDD = 2.5V ± 0.2V
* Data rate: 333Mbps/266Mbps (max.)
* Double Data Rate architecture; two data transfers per clock cycle.

The EDD1232AAFA is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined a.

EDD1232AABH

EDD1232ABBH

EDD12322GBH-TS

EDD1204ALTA

EDD1208ALTA

EDD1216AASE

EDD1216AATA

EDD1216ALTA

EDD10161BBH-TS

EDD10163BBH-LS

EDD10321BBH-TS

EDD10323BBH-LS

EDD11