74F114 Datasheet - Fairchild Semiconductor

Dual JK Negative Edge-Triggered Flip-Flop

74F114 General Description

The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the .

74F114 Datasheet (55.22 KB)

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Part number:

74F114

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Fairchild Semiconductor

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55.22 KB

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Dual jk negative edge-triggered flip-flop.
74F114 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised August 1999 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks .

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74F114 Dual Negative Edge-Triggered Flip-Flop Fairchild Semiconductor

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74F114 General Description

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