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74F114 - Dual JK Negative Edge-Triggered Flip-Flop

Description

The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs.

Synchronous state changes are initiated by the falling edge of the clock.

Triggering occurs at a voltage level of the clock and is not directly related to the transition time.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74F114 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised August 1999 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively.
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